full end-to-end digital synthesis flow for VLSI ASIC designs
Project homepage: http://opencircuitdesign.com/qflow/
Description
A digital synthesis flow is a set of tools and methods used to turn a
VLSI design written in a high-level behavioral language like Verilog
or VHDL into a physical circuit, which can either be configuration code
for an FPGA target or a layout in a specific technology, that would
become part of an IC.
Qflow uses a complete and open source tool chain for synthesizing
digital circuits starting from Verilog source and ending in physical
layout for a specific target fabrication process.
Package information
- Ports path
- cad/qflow
- Package architecture
- amd64
- Maintainer
- Alessandro De Laurenzis <just22@atlantide.mooo.com>
- Categories
- cad, lang/tcl, lang/python
- Available flavors
- None listed
- Only for architectures
- aarch64, amd64, arm, i386, mips64, mips64el, powerpc, powerpc64, riscv64, sparc64, alpha, hppa
Ports list build and test dependencies as well as runtime dependencies. pkg_add selects those needed for installation.
Direct dependencies
Runtime
- lang/tcl/8.5 tcl->=8.5,<8.6
- lang/python/3,-tkinter
- cad/yosys
- cad/graywolf
- cad/opensta
- cad/qrouter
- cad/magic
- cad/netgen
- shells/tcsh
- sysutils/ggrep
- lang/python/3
Build
- lang/tcl/8.5 tcl->=8.5,<8.6
- cad/yosys
- cad/graywolf
- cad/opensta
- cad/qrouter
- cad/magic
- cad/netgen
- lang/python/3
- devel/gmake