opensta-2.2.0p2
Parallax Static Timing Analyzer
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Description
OpenSTA is a gate level static timing verifier. As a stand-alone
executable it can be used to verify the timing of a design using
standard file formats:
- Verilog netlist
- Liberty library
- SDC timing constraints
- SDF delay annotation
- SPEF parasitics
OpenSTA uses a TCL command interpreter to read the design, specify
timing constraints and print timing reports.
Package information
- Ports path
- cad/opensta
- Package architecture
- amd64
- Maintainer
- Alessandro De Laurenzis <just22@atlantide.mooo.com>
- Categories
- cad, lang/tcl
- Available flavors
- None listed
- Only for architectures
- aarch64, amd64, arm, i386, mips64, mips64el, powerpc, powerpc64, riscv64, alpha, hppa, sparc64
These are ports metadata. Binary availability depends on the release, architecture and mirror. Build and test dependencies are not an installation checklist.
Direct dependencies
Library
- lang/tcl/8.6 tcl->=8.6,<8.7
- devel/cudd
Build
- devel/bison
- devel/swig
- lang/tcl/8.6 tcl->=8.6,<8.7
- devel/cmake/core STEM->=4
- devel/ninja
Used by (2 dependency relationships)
Includes library, runtime, build and test relationships. Results load 100 at a time.