tool for netlist comparison (LVS) and format manipulation
Project homepage: http://opencircuitdesign.com/netgen/
Description
Netgen is a tool for comparing netlists, a process known as LVS (Layout
vs. Schematic). This is an important step in the VLSI IC design flow,
ensuring that the geometry that has been laid out matches the expected
circuit.
Netgen is considered complete and competitive with commercial-grade
tools. Code was added to handle device properties and to resolve
parallel combinations of devices whether individually instantiated
or implied through the use of the "M" property. Serial and parallel
networks of passive devices are analyzed and compared between networks.
Package information
- Ports path
- cad/netgen
- Package architecture
- amd64
- Maintainer
- Alessandro De Laurenzis <just22@atlantide.mooo.com>
- Categories
- cad, x11/tk, lang/python, lang/tcl
- Available flavors
- None listed
- Only for architectures
- aarch64, amd64, arm, i386, mips64, mips64el, powerpc, powerpc64, riscv64, sparc64, alpha, hppa
Ports list build and test dependencies as well as runtime dependencies. pkg_add selects those needed for installation.
Direct dependencies
Library
- x11/tk/8.5 tk->=8.5,<8.6
- lang/tcl/8.5 tcl->=8.5,<8.6
Runtime
Build
Used by (2 dependency relationships)
Includes library, runtime, build and test dependencies.