system for sequential logic synthesis and verification
Project homepage: https://people.eecs.berkeley.edu/~alanmi/abc
Description
ABC is a growing software system for synthesis and verification of binary
sequential logic circuits appearing in synchronous hardware designs. ABC
combines scalable logic optimization based on And-Inverter Graphs (AIGs),
optimal-delay DAG-based technology mapping for look-up tables and standard
cells, and innovative algorithms for sequential synthesis and verification.
Package information
- Ports path
- cad/abc
- Package architecture
- amd64
- Maintainer
- Alessandro De Laurenzis <just22@atlantide.mooo.com>
- Categories
- cad
- Available flavors
- None listed
- Only for architectures
- aarch64, amd64, arm, i386, mips64, mips64el, powerpc, powerpc64, riscv64, sparc64, alpha, hppa, m88k, sh
Ports list build and test dependencies as well as runtime dependencies. pkg_add selects those needed for installation.