{"schema_version":1,"metadata":{"branch":"release","release":"8.0","architecture":"amd64","generated_at":"2026-10-21T02:35:53.703506+00:00","source_url":"https://cdn.openbsd.org/pub/OpenBSD/8.0/packages/amd64/sqlports-7.55.tgz","source_sha256":"393d2bd6f5b23c8ba1809ec63f3e8310d7787d329b7350089609a078eb01a387","package_count":12098,"source_kind":"sqlports"},"package":{"name":"graywolf-0.1.6p2","path":"cad/graywolf","url":"/packages/release/cad/graywolf/","comment":"placement tool used in VLSI design","homepage":"https://github.com/rubund/graywolf","maintainer":"Alessandro De Laurenzis <just22@atlantide.mooo.com>","description":"graywolf is a program for placement of VLSI digital circuits, mainly\nintended as part of qflow tool-chain\n(http://opencircuitdesign.com/qflow/).\n\nIt is a fork of the last open-source version of TimberWolf (which is now\ncommercial software) and has been modified to streamline the build\nprocess and make it behave more as a standard command-line tool.\n\nIt is based on the general combinatorial optimization technique known as\nsimulated annealing and is suitable for standard cell, macro/custom\ncell, and gate-array professional-grade placement.\n","description_source":null,"description_unresolved":[],"package_architecture":"amd64","stem":"graywolf","readme":null,"dependencies":[{"path":"devel/gsl","type":"library","package_spec":"","url":"/packages/release/devel/gsl/"},{"path":"devel/cmake/core","type":"build","package_spec":"STEM->=4","url":"/packages/release/devel/cmake/core/"},{"path":"devel/ninja","type":"build","package_spec":"","url":"/packages/release/devel/ninja/"}],"reverse_dependencies":{"count":2,"url":"/packages/data/09/092d2c32185c8834d2937527a01d51d68730cab226b3de9d0e214f45f537ccb0.json"},"categories":["cad"],"flavors":[],"only_for_architectures":[],"not_for_architectures":[]}}