{"schema_version":1,"metadata":{"branch":"current","release":"7.9","architecture":"amd64","generated_at":"2026-09-09T04:04:41.004595+00:00","source_url":"https://cdn.openbsd.org/pub/OpenBSD/snapshots/packages/amd64/sqlports-7.55.tgz","source_sha256":"fcdbba1b9df747882aa9bab4af20ebec8dac10655069c90f1cd4145c06e1235e","package_count":12031,"source_kind":"sqlports"},"package":{"name":"graywolf-0.1.6p2","path":"cad/graywolf","url":"/packages/current/cad/graywolf/","comment":"placement tool used in VLSI design","homepage":"https://github.com/rubund/graywolf","maintainer":"Alessandro De Laurenzis <just22@atlantide.mooo.com>","description":"graywolf is a program for placement of VLSI digital circuits, mainly\nintended as part of qflow tool-chain\n(http://opencircuitdesign.com/qflow/).\n\nIt is a fork of the last open-source version of TimberWolf (which is now\ncommercial software) and has been modified to streamline the build\nprocess and make it behave more as a standard command-line tool.\n\nIt is based on the general combinatorial optimization technique known as\nsimulated annealing and is suitable for standard cell, macro/custom\ncell, and gate-array professional-grade placement.\n","package_architecture":"amd64","stem":"graywolf","readme":null,"dependencies":[{"path":"devel/gsl","type":"library","package_spec":"","url":"/packages/current/devel/gsl/"},{"path":"devel/cmake/core","type":"build","package_spec":"STEM->=4","url":"/packages/current/devel/cmake/core/"},{"path":"devel/ninja","type":"build","package_spec":"","url":"/packages/current/devel/ninja/"}],"reverse_dependencies":{"count":2,"url":"/packages/data/0a/0ac727a505c5460e5739e1e33375b81738b4df99c0e024a26ee8231a72e5c293.json"},"categories":["cad"],"flavors":[],"only_for_architectures":[],"not_for_architectures":[]}}