{"schema_version":1,"metadata":{"branch":"release","release":"7.9","architecture":"amd64","generated_at":"2026-09-09T04:04:02.361425+00:00","source_url":"https://cdn.openbsd.org/pub/OpenBSD/7.9/packages/amd64/sqlports-7.54.tgz","source_sha256":"2de00144847bf9da3a365be982f101dbb55d591ed7a915ea94984a16ab0e0404","package_count":12059,"source_kind":"sqlports"},"package":{"name":"yosys-0.9pl4081p4","path":"cad/yosys","url":"/packages/release/cad/yosys/","comment":"framework for Verilog RTL synthesis","homepage":"http://www.clifford.at/yosys/","maintainer":"Alessandro De Laurenzis <just22@atlantide.mooo.com>","description":"Yosys Open SYnthesis Suite\n\nYosys is a framework for Verilog RTL synthesis. It currently has extensive\nVerilog-2005 support and provides a basic set of synthesis algorithms for\nvarious application domains. Selected features and typical applications:\n\n- Process almost any synthesizable Verilog-2005 design\n- Converting Verilog to BLIF / EDIF/ BTOR / SMT-LIB / simple RTL Verilog / etc.\n- Built-in formal methods for checking properties and equivalence\n- Mapping to ASIC standard cell libraries (in Liberty File Format)\n- Mapping to Xilinx 7-Series and Lattice iCE40 FPGAs\n- Foundation and/or front-end for custom flows\n\nYosys can be adapted to perform any synthesis job by combining the existing\npasses (algorithms) using synthesis scripts and adding additional passes as\nneeded by extending the Yosys C++ code base.\n","package_architecture":"amd64","stem":"yosys","readme":null,"dependencies":[{"path":"lang/tcl/8.5","type":"library","package_spec":"tcl->=8.5,<8.6","url":"/packages/release/lang/tcl/8.5/"},{"path":"devel/libffi","type":"library","package_spec":"","url":"/packages/release/devel/libffi/"},{"path":"cad/abc","type":"runtime","package_spec":"","url":"/packages/release/cad/abc/"},{"path":"math/graphviz","type":"runtime","package_spec":"","url":"/packages/release/math/graphviz/"},{"path":"graphics/xdot","type":"runtime","package_spec":"","url":"/packages/release/graphics/xdot/"},{"path":"shells/bash","type":"runtime","package_spec":"","url":"/packages/release/shells/bash/"},{"path":"lang/python/3","type":"runtime","package_spec":"","url":"/packages/release/lang/python/3/"},{"path":"devel/bison","type":"build","package_spec":"","url":"/packages/release/devel/bison/"},{"path":"shells/bash","type":"build","package_spec":"","url":"/packages/release/shells/bash/"},{"path":"lang/python/3","type":"build","package_spec":"","url":"/packages/release/lang/python/3/"},{"path":"devel/gmake","type":"build","package_spec":"","url":"/packages/release/devel/gmake/"},{"path":"cad/yosys","type":"test","package_spec":"","url":"/packages/release/cad/yosys/"},{"path":"cad/abc","type":"test","package_spec":"","url":"/packages/release/cad/abc/"},{"path":"lang/gawk","type":"test","package_spec":"","url":"/packages/release/lang/gawk/"},{"path":"lang/iverilog","type":"test","package_spec":"","url":"/packages/release/lang/iverilog/"},{"path":"shells/bash","type":"test","package_spec":"","url":"/packages/release/shells/bash/"},{"path":"lang/python/3","type":"test","package_spec":"","url":"/packages/release/lang/python/3/"}],"reverse_dependencies":{"count":3,"url":"/packages/data/e2/e24c29701ad4cb614f931becaa70bad898f0c8c0df1a8524fbb8f63e3446191f.json"},"categories":["cad","lang/python","lang/tcl"],"flavors":[],"only_for_architectures":["aarch64","amd64","arm","i386","mips64","mips64el","powerpc","powerpc64","riscv64","alpha","hppa","sparc64"],"not_for_architectures":[]}}
