{"schema_version":1,"metadata":{"branch":"release","release":"7.9","architecture":"amd64","generated_at":"2026-09-09T04:04:02.361425+00:00","source_url":"https://cdn.openbsd.org/pub/OpenBSD/7.9/packages/amd64/sqlports-7.54.tgz","source_sha256":"2de00144847bf9da3a365be982f101dbb55d591ed7a915ea94984a16ab0e0404","package_count":12059,"source_kind":"sqlports"},"package":{"name":"qflow-1.4.83p4","path":"cad/qflow","url":"/packages/release/cad/qflow/","comment":"full end-to-end digital synthesis flow for VLSI ASIC designs","homepage":"http://opencircuitdesign.com/qflow/","maintainer":"Alessandro De Laurenzis <just22@atlantide.mooo.com>","description":"A digital synthesis flow is a set of tools and methods used to turn a\nVLSI design written in a high-level behavioral language like Verilog\nor VHDL into a physical circuit, which can either be configuration code\nfor an FPGA target or a layout in a specific technology, that would\nbecome part of an IC.\nQflow uses a complete and open source tool chain for synthesizing\ndigital circuits starting from Verilog source and ending in physical\nlayout for a specific target fabrication process.\n","package_architecture":"amd64","stem":"qflow","readme":null,"dependencies":[{"path":"lang/tcl/8.5","type":"runtime","package_spec":"tcl->=8.5,<8.6","url":"/packages/release/lang/tcl/8.5/"},{"path":"lang/python/3,-tkinter","type":"runtime","package_spec":"","url":"/packages/release/lang/python/3,-tkinter/"},{"path":"cad/yosys","type":"runtime","package_spec":"","url":"/packages/release/cad/yosys/"},{"path":"cad/graywolf","type":"runtime","package_spec":"","url":"/packages/release/cad/graywolf/"},{"path":"cad/opensta","type":"runtime","package_spec":"","url":"/packages/release/cad/opensta/"},{"path":"cad/qrouter","type":"runtime","package_spec":"","url":"/packages/release/cad/qrouter/"},{"path":"cad/magic","type":"runtime","package_spec":"","url":"/packages/release/cad/magic/"},{"path":"cad/netgen","type":"runtime","package_spec":"","url":"/packages/release/cad/netgen/"},{"path":"shells/tcsh","type":"runtime","package_spec":"","url":"/packages/release/shells/tcsh/"},{"path":"sysutils/ggrep","type":"runtime","package_spec":"","url":"/packages/release/sysutils/ggrep/"},{"path":"lang/python/3","type":"runtime","package_spec":"","url":"/packages/release/lang/python/3/"},{"path":"lang/tcl/8.5","type":"build","package_spec":"tcl->=8.5,<8.6","url":"/packages/release/lang/tcl/8.5/"},{"path":"cad/yosys","type":"build","package_spec":"","url":"/packages/release/cad/yosys/"},{"path":"cad/graywolf","type":"build","package_spec":"","url":"/packages/release/cad/graywolf/"},{"path":"cad/opensta","type":"build","package_spec":"","url":"/packages/release/cad/opensta/"},{"path":"cad/qrouter","type":"build","package_spec":"","url":"/packages/release/cad/qrouter/"},{"path":"cad/magic","type":"build","package_spec":"","url":"/packages/release/cad/magic/"},{"path":"cad/netgen","type":"build","package_spec":"","url":"/packages/release/cad/netgen/"},{"path":"lang/python/3","type":"build","package_spec":"","url":"/packages/release/lang/python/3/"},{"path":"devel/gmake","type":"build","package_spec":"","url":"/packages/release/devel/gmake/"}],"reverse_dependencies":{"count":0,"url":null},"categories":["cad","lang/tcl","lang/python"],"flavors":[],"only_for_architectures":["aarch64","amd64","arm","i386","mips64","mips64el","powerpc","powerpc64","riscv64","alpha","hppa","sparc64"],"not_for_architectures":[]}}