verilator-5.044
very fast free Verilog HDL simulator
Back to search · Project homepage
Description
Verilator is the fastest free Verilog HDL simulator, and beats most
commercial simulators. It compiles synthesizable Verilog (not test-bench
code!), plus some PSL, SystemVerilog and Synthesis assertions into C++
or SystemC code. It is designed for large projects where fast simulation
performance is of primary concern, and is especially well suited to
generate executable models of CPUs for embedded software design teams.
Package information
- Ports path
- lang/verilator
- Package architecture
- amd64
- Maintainer
- The OpenBSD ports mailing-list <ports@openbsd.org>
- Categories
- lang, devel
- Available flavors
- None listed
- Only for architectures
- aarch64, amd64, arm, i386, mips64, mips64el, powerpc, powerpc64, riscv64, sparc64, alpha, hppa, m88k, sh
These are ports metadata. Binary availability depends on the release, architecture and mirror. Build and test dependencies are not an installation checklist.