myhdl-0.11.51
Python as a hardware description and verification language
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Description
MyHDL is an open source Python package that lets you go from Python to
silicon. With MyHDL, you can use Python as a hardware description and
verification language. Furthermore, you can convert MyHDL code, that was
developed towards implementation, to Verilog and VHDL automatically, and
take it to a silicon implementation from there.
Package information
- Ports path
- lang/myhdl
- Package architecture
- amd64
- Maintainer
- The OpenBSD ports mailing-list <ports@openbsd.org>
- Categories
- lang, lang/python
- Available flavors
- None listed
- Only for architectures
- aarch64, amd64, arm, i386, mips64, mips64el, powerpc, powerpc64, riscv64, sparc64, alpha, hppa
These are ports metadata. Binary availability depends on the release, architecture and mirror. Build and test dependencies are not an installation checklist.
Direct dependencies
Runtime
Build
- lang/python/3
- devel/py-build
- devel/py-installer
- devel/py-setuptools py3-setuptools->=79v0
- devel/py-wheel