Yosys Open SYnthesis Suite
Project homepage: https://github.com/YosysHQ
Description
This is a framework for RTL synthesis tools. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.
Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the yosys C++ code base.
Package information
- Ports path
- cad/yosys
- Package architecture
- amd64
- Maintainer
- Thomas Dettbarn <dettus@dettus.net>
- Categories
- cad, lang/python
- Available flavors
- None listed
- Only for architectures
- aarch64, amd64, arm, i386, mips64, mips64el, powerpc, powerpc64, riscv64, sparc64, alpha, hppa
Ports list build and test dependencies as well as runtime dependencies. pkg_add selects those needed for installation.
Direct dependencies
Library
Runtime
Build
Test
OpenBSD README
+-------------------------------------------------------------------------------
| Running yosys on OpenBSD
+-------------------------------------------------------------------------------
High RAM consumption
====================
Synthesizing FPGAs is a memory intensive task. Even relatively small designs
might lead to errors such as
libc++abi: terminating due to uncaught exception of type std::bad_alloc
Abort trap (core dumped)
In this case, editing /etc/login.conf(5), to increase the parameters
default:\
datasize-max=8192M:\
datasize-cur=8192M
helps. Obviously, it is required to log off and on again, before it has any
effect on re-running YoSys.
Used by (2 dependency relationships)
Includes library, runtime, build and test dependencies.