abc-1.01.20210519
system for sequential logic synthesis and verification
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Description
ABC is a growing software system for synthesis and verification of binary
sequential logic circuits appearing in synchronous hardware designs. ABC
combines scalable logic optimization based on And-Inverter Graphs (AIGs),
optimal-delay DAG-based technology mapping for look-up tables and standard
cells, and innovative algorithms for sequential synthesis and verification.
Package information
- Ports path
- cad/abc
- Package architecture
- amd64
- Maintainer
- Alessandro De Laurenzis <just22@atlantide.mooo.com>
- Categories
- cad
- Available flavors
- None listed
- Only for architectures
- aarch64, amd64, arm, i386, mips64, mips64el, powerpc, powerpc64, riscv64, sparc64, alpha, hppa, m88k, sh
These are ports metadata. Binary availability depends on the release, architecture and mirror. Build and test dependencies are not an installation checklist.
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